As illustrated in FIGS. 11 (a) and 11 (b), a conventional liquid crystal display device uses a lot of thin-film elements, each of which includes, on a substrate, a lower electrode 101, an insulating layer 102, and an upper electrode 103. The thin-film elements are used as a pixel auxiliary capacitor 101. At the same time, a pixel TFT (Thin-film Transistor) also uses such a thin-film element including a lower electrode 101, an insulating layer 102, and an upper electrode 103 as illustrated in FIG. 11(a) and FIG. 11 (c).
The thin-film elements of such configuration are provided not only in the liquid crystal display device, but also in a data storing memory cell. For example, Japanese Unexamined Patent Application Publication No. 4-274359 (published on Sep. 30, 1992)(hereinafter, referred to as Patent Document 1) discloses, as illustrated in FIG. 12, a configuration including a lower capacitor electrode 151, which acts as a lower electrode, an insulating layer, which is not illustrated in the figure, and an upper capacitor 152, which acts as an upper electrode.
Incidentally, in the case where the thin-film element including the lower electrode 101, the insulating layer 102, the upper electrode 103 is formed as illustrated in FIGS. 11(a) and 11(b), the upper electrode 103 cannot be drawn over a same layer without being extended over an edge of the lower electrode 101.
As a result, a part of the upper electrode 103 is raised at an edge 101a of the lower electrode 101. Thereby, the insulating layer 102 does not efficiently cover the edge 101a of the lower electrode 101, then breakdown voltage falls. As a result, in a high-voltage charged capacitor, leakage is caused at the upper electrode 103 and the upper electrode 101 by dielectric breakdown.
Japanese Unexamined Patent Application Publication No. 61-264740 (published on 22 Nov., 1986)(hereinafter, referred to as Patent Document 2) also concretely discloses this issue. FIGS. 13(a) to 13 (h) illustrate a conventional fabrication process, which is disclosed in Patent Document 2.
That is, Patent Document 2 discloses that, as illustrated in FIG. 13 (e), effects of inner distortion caused by heat stress etc. tend to cause projection at edge portions (B) of a vertically etched first layer polysilicon gate electrode 201 and a second gate oxide film 202 formed by heat oxidization on the first layer polysilicon gate electrode 201, while the second gate oxide film 202 (B′) tends to be extremely thinned near a first gate oxide film 203 by the same effects.
Moreover, FIG. 13 (f) illustrates a step for forming a second layer polysilicon gate electrode 204 on the second gate oxide film 202-202′: firstly forming about 3000A of a second layer polysilicon film by an LPCVD technique and then diffusing phosphorus on the second layer polysilicon film. In this step, an edge of the second layer polysilicon gate electrode 204 is overhung (i.e., having a portion (C)) by effects of the projected peripheral part (B) and the thinner part (B′) illustrated in FIG. 13(e). As a result, enough breakdown voltage cannot be attained between the first layer polysilicon gate electrode 201 and the second layer polysilicon gate electrode 204. Exceeding the breakdown voltage causes leakage between the first layer polysilicon gate electrode 201 and the second layer polysilicon gate electrode 204.
Patent Document 2 discloses a solution for the issue. As illustrated in FIGS. 14 (a) to 14 (h), the edge of the first layer polysilicon gate electrode 201 is etched in a tapered shape, whereby the second gate oxide film 202 will not have an overhung shape and also have a smoother surface. As a result, the first layer polysilicon gate electrode 201 is covered sufficiently. Thereby, it is possible to obtain enough breakdown voltage in between the first layer polysilicon gate electrode 201 and the second layer polysilicon gate electrode 204.
However, when fabricating a TFT with the conventional thin-film elements, in which the first layer polysilicon gate electrode 201 as a lower electrode is formed with the tapered edge as disclosed in Patent Document 2, a different issue is caused. That is, a difference in thickness between a central part and an edge of the lower electrode causes a difference in dope concentration in the lower electrode. As a result, a threshold property of the TFT becomes different between the central part of the lower electrode and the edge of the lower electrode, and then the edge acts as a parasitic transistor, thereby deteriorating the TFT in property.